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Last month, a team from Google protection Researchers have released a tool that can adjust the accurate code of AMD processors based on Microarching Zen architecture, Zintol. While this is a security vulnerability, for some, this is an opportunity; Chinese members Jiashin Project They run a goal with a goal Develop a small symbol of the ZEN modern CPU to make it implement the RISC-V programs. The ultimate goal can be to eventually build the CPU using RISC-V using already available silicone.
X86 is a complex educational instructions (CISC) (CISC) that has been developed about 48 years ago. However, internally, the modern X86 nuclei relies on the ownership engines that operate the computer of RISC ISA to deal with complex instructions. ISAS RICC is not documented, but it should be generally similar to the well-known ISA RICSC, such as ARM or RISC-V. CPU Microcode is a low -level layer that translates CISC instructions into simple internal instructions that resemble RICSC. Microcode CPU is supposed to be adjusted only by the CPU seller, but sometimes this is not the case, and it seems that some parts of the Microcode Zen 1/2/3/4 icon from AMD can be changed using Zentool.
Jianchen project members want to find someone, can modify the AMD MicroCode icon on a modern processor-for example, a series of EPYC 9004-to implement RISC-V. The correction is expected to either enable the direct implementation of RISC-V programs or significantly increase the speed of operating time compared to the metaphor using the same devices. The work should be tested using RISC-V versions of Standards Like CoreMark or Dhrystone. Full submission includes binary or software instructions, composition files, dependencies, and test instructions. If only diodes are presented before the deadline on June 6, the identical source code must be added via the withdrawal request later. The winner will receive 20,000 yenno (about $ 2,735).
The AMD series of EPYC 9004 and similar treatments offer the basic performance and indiscriminate charges on the processors currently available on the RISC-V basis, so the implementation of RISC-V on EPYCS is a reasonable idea. However, the accurate code to fix the internal errors is designed instead of replacing ISA the front end, but it is not clear whether the accurate code can be fully rewritten, and the people on Ycombinator male.
Once again in mid-2010, AMD planned to introduce CPUS X86-64 and ARMV8-A Zen (something I was recently summoned Written by Mike Clark, the chief architect in AMD), so it is very likely that there will be a small symbol of Zen 1 architectural engineering that supported ISA Aarch64 front. However, the Zen 1 CPU can be characterized by several “holes” holes, one that supports X86-64 and another ARCH64. We doubt that this is the case although modern central processing units have comprehensive improvements in the performance of devices that include solid wire improvements between the exact symbol and the rest of the nucleus. AMD has barely developed a small symbol that supports ARCH64 or RISC-V for Zen 2/3/4 processors, so the exact code layer of the central processing units is with the resolution of x86-64 and there is not enough of the exact symbol to rewrite them from scratching.
“This is not achieved,” his name is one of the commentators Monocase Books. “Not enough of the accurate re -writing symbol to do this even as a very slow penetration. Even if all the microscopic codes are rewriting, the accurate symbol is a kind of reserve path on the modern X86 cores with the fast track as it is the solid solid of the X86 format. Not a leader.”
One of the commentators criticized the coordination of the competition, indicating that it is a way to complete a complex work with less than $ 3,000.
In general, while the concept of accurate code re -configuration is an interesting concept and stimulates the debate about alternative central treatment unit designs, multiple ISA support, low -level improvement, it does not seem that the competition will achieve the declared goal. Perhaps, rewriting (or rather re-assembles) RISC-V or two for CPUS X86 more logical?
